Serial interfaces are well-known in personal computer, or the like. Such serial interfaces comprise a so-called UART (Universal Asynchronous Receiver Transmitter) for generating an asynchronous bit stream comprised of data words, usually bytes, preceded by a START-bit and succeeded by a STOP-bit. The baud rate of such an asynchronous bit stream may vary. Pulse signals comprised in the bit stream can be distorted by noise picked up by a transmission line via which the bit stream is conveyed to a device receiving the asynchronous bit stream. The receiving device, which first synchronizes itself to the received bit stream, checks whether pulse signals comprised in the bit stream are within given specifications, i.e., checks the accuracy of the wave form of the pulse. The receiving device usually comprises synchronous circuitry comprised of flip flops and gate circuits. A problem might arise if, for some reason, e.g., to achieve power savings, a system clock signal of the receiving device is half the clock frequency of the personal computer generating the asynchronous bit stream. Then, a detector comprised in the receiving device cannot accurately detect whether the pulse signal is within the required specifications. So, what is needed is a baud rate detector having double resolution.
For other purposes, some form of double resolution schemes are known.
In the article "Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits", M.
Afghahi et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, August 1991, pp. 1168-1170, discloses a double edge-triggered flip flop which responds to both edges of a clock pulse. Such a double edge-triggered flip flop can be used in a repeater inserted in a long transmission line.
In the article "Clocking Schemes for High-Speed Digital Systems", S. H. Unger et al., IEEE Transactions on Computers, Vol. C-35, No. 10, October 1986, pp. 880-895, discloses the use of double edge-triggered D-flip flops in a clocking scheme for a high speed digital system.
In the U.S. Pat. No. 5,703,838 a Vernier delay line interpolator to be used with a coarse counter clocked by a clock signal is disclosed for measuring time intervals. By delaying a clock signal in a multiple-tapped delay line, an interpolator is obtained to be used for measuring signal time intervals with a resolution higher than the resolution of the clock signal used in the timing interval detector. Such a combination of a coarse counter and a delay line interpolator can be used in time of flight measurements to infer a particle type. Typically, resolutions as low as 25 picoseconds can be obtained.
In the Article, "1994 Symposium on VLSI Circuits", Honolulu, Digest of Technical Papers, pp. 43-44, a high speed interface is disclosed for a multiprocessor interconnection network. To achieve higher transfer rates, among other measures, sampling of data is done on both edges of a clock signal. A receiver phase shifts a transmitter clock by 90.degree. and uses both edges to sample incoming data.